This virtual computer allows us to approach the nature of systems software. With this computer we will study various aspects of systems software for controlling the machine and for translating codes from more human readable form to machine readable form. The basic architecture for the machine is shown in the figure below.
The CPU is comprised of 8, 16-bit programmer-visible registers, a 16-bit program counter (PC), a flag register, an I/O port register (4 bits), an interrupt decode register (4 bits), an acknowledge bit, a 32-bit instruction register and an arithmetic/logic unit (ALU). Additionally there is an internal 8-bit bus for all signals (address, data and control). Details of control have been suppressed to emphasize the essential features pertinent to systems programming. The memory is a 64k space of byte organized cells. The figure shows a layout for memory composed of a 2k ROM (read only memory) and 62k of RAM (volitile random access memory). Shown is a map of regions used for various system purposes. The boot and BIOS (basic input/output system) occupy ROM. from location 0 to 2048d. The next 32 bytes are dedicated to an interrupt vector table. Next an approximate area dedicated to the BDOS (basic disk operating system). The reason this area is approximate is that different versions of the OS occupy different amounts of space. The largest area is devoted to user programs (USR). This area is also approximate since it is sandwiched between the BDOS and the system stack area. Extra care is needed in establishing the boundries of these areas and making sure the user program does not extend into either of the other two areas.
The first five registers, A, B, C, D, E are general purpose, except that A is used as the accumulator. All arithmetic/logic operations results are sent to the A register. The rest of the registers are special purpose (e.g. IX for indexed addressing, BP for base addressing, and SP for stack pointer) The E register is an extra 16-bit register which is used as an adjunct to the accumulator (A) for multiplication and division arithmetic operations for double precision results.
The following instruction set is a subset of the possible instructions. This set does not include the richer addressing modes that are available in SimpComp. This subset just allows us to address fundamental programming constructs. Later we will expand the instruction set to include all of the addressing modes and extra "features" of the computer.
r = A, B, C, D, E, IX, BP, SP
r' = r; F (flags, Int and I/O word)
rH =
the high order 8 bits of register r, rL is the low order 8 bits of register r.
These designations are required to designate the destination or source for 8-bit
data.
The symbol, #, means an immediate operand.
M stands for memory.
The []
brackets indicate an address value, addr.
neg = negative flag
carry =
carry flag
ovfl = overflow flag
zero = zero flag
You can see the complete instruction format and instruction set for the SimpComp here. The instruction set given here is the subset of instructions that eliminates byte-oriented load and store operations. It also eliminates the more advanced addressing modes available in the full instruction set. These are the instructions you will implement.
| Instruction | Semantics | Example | Bytes | Hex |
| Load and Store | ||||
| LD r, addr | rH <- M[addr]; rL <- M[addr+1] | LD C, COUNTER | 4 | 87 |
| ST r, addr | M[addr] <- rH; M[addr+1] <- rL | ST A, RESULT | 4 | B7 |
| LD r, #immed | rH <- immedH; rL <- immedL | LD D, #ONE_HUNDRED | 4 | 8F |
| LD r, r1 | rH <- M[r1]; rL <- M[r1+1] | LD D, B | 2 | F5 |
| ST r, r1 | M[r1] <- rH; M[r1+1] <- rL | ST A, B | 2 | FD |
| MOV r1, r2 | r1 <- r2 | MOV D, A | 2 | B5 |
| Arithmetic Logic | ||||
| ADD r1, r2 | A <- r1 + r2 | ADD A, D | 2 | 01 |
| SUB r1, r2 | A <- r1 - r2; carry <- neg | SUB B, C | 2 | 09 |
| AND r1, r2 | A <- r1 & r2 | AND B, D | 2 | 11 |
| OR r1, r2 | A <- r1 | r2 | OR B, D | 2 | 15 |
| XOR r1, r2 | A <- r1 ^ r2 | XOR B, D | 2 | 19 |
| NOT r1 | A <- ~r1 | NOT A | 2 | 1D |
| Data Manipulation | ||||
| SHL r1 | A <- r1 * 2; carry <- ovfl | SHL D | 2 | 21 |
| SHR r1 | A <- r1 / 2; carry <- unfl | SHR D | 2 | 25 |
| Flow Control | ||||
| JMP r | PC <- r | JMP D | 2 | 41 |
| JMP immed | PC <- immed | JMP LOOP1 | 3 | 42 |
| JMPx r [x=Z,C,N,O] | IF (x) PC <- r | JMPZ D JMPC D JMPN D JMPO D |
2 | 45 49 4D 46 |
| JMPx immed | IF (x) PC <- immed | JMPZ LOOP1 JMPC LOOP1 JMPN LOOP1 JMPO LOOP1 |
3 | 4E 52 56 5A |
| CALL r | push(PC); PC <- r | CALL D | 2 | 51 |
| CALL immed | push(PC); PC <- immed | CALL CHECK_RESULT | 3 | 5E |
| RET | PC <- POP() | RET | 1 | 50 |
| PUSH r | M[SP]<- r'H; SP <- SP+1; M[SP]<- r'L; SP <- SP+1 | PUSH A | 2 | 55 |
| POP r' | SP <- SP-1; r'L <-M[SP]; SP <- SP-1; r'H <-M[SP] | POP A | 2 | 5D |
| I/O | ||||
| IN r | rL <- Port[port] | IN B | 2 | 69 |
| OUT r | Port[port] <- rL | OUT B | 2 | 6D |
| SETP immed | FLAGS[0..3] <- immed[0..3] | SETP 3 | 2 | 71 |
| Miscellaneous | ||||
| NOP | no operation | NOP | 1 | 00 |
| HALT | stops the computer (run bit <- 0) | HALT | 1 | 04 |
The specifications for the assembly language and formats for the SimpComp can to be used for the project are located here.