Format 0: load 1 byte
|
Opcode 00 |
Format 1: load 2 bytes, register designators
|
Opcode 01 |
dest.,R1 |
src., R2 |
Format 2: load 2 bytes, immediate byte operand
|
Opcode 01 |
immediate |
Format 3: load 3 bytes, immediate word operand
|
Opcode 10 |
immediate high |
immediate low |
Format 4: load 4 bytes, register designation, immediate operand
|
Opcode 11 |
R1 |
R2 |
immediate high |
immediate low |
Opcode:
Bit 7: 0 = all non-load/store instructions, 1 = load/store instruction
Bit 2, if bit 7 = 1: 0 = byte mode, 1 = word mode
Bits 0,1: Byte count
00 = 1
01 = 2
10 = 3
11 = 4
Registers
Bits 0..3: source register or operand2
Bits 4..7: destination register or operand1
|
MNEMON |
OPNDS |
SEMANTICS |
BYTE |
BIT PAT |
HEX |
Load/Store |
|
|
|
|
|
|
LDB |
R,
addr |
RL
<- M[addr]
direct |
4 |
1000
0011 |
83 |
|
LD |
R,
addr |
RH
<- M[addr]; RL<-M[addr+1] |
4 |
1000
0111 |
87 |
|
LDB |
R,
#opnd |
RL
<- immed
immed |
3 |
1000
1010 |
8A |
|
LD |
R,
#opnd |
RH<-
immedH; RL<- immedL |
4 |
1000
1111 |
8F |
|
LDB |
R,
R1 |
RL<-M[R1]
register |
2 |
1111
0001 |
F1 |
|
LD |
R,
R1 |
RH<-M[R1];
RL<-M[R1+1] |
2 |
1111
0101 |
F5 |
|
LDB |
R,
X |
RL<-M[IX];
IX++
indexed |
2 |
1000
0001 |
81 |
|
LD |
R,
X |
RH<-M[IX];
IX++; RL<-M[IX]; IX++ |
2 |
1000
0101 |
85 |
|
LDB |
R,
+offset |
RL<-M[B+offset]
base-offset |
4 |
1000
1011 |
8B |
|
LD |
R,
+offset |
RH<-M[B+offset];
RL<-M[B+offset+1] |
4 |
1001
0111 |
97 |
|
LDB |
R,
+[R1] |
RL<-M[B+R1]
base-register |
2 |
1000
1001 |
89 |
|
LD |
R,
+[R1] |
RH<-M[B+R1];
RL<-M[B+R1+1] |
2 |
1001
0101 |
95 |
|
LDB |
R,
@LOC |
RL<-M[M[LOC]]
indirect-immed |
4 |
1001
1011 |
9B |
|
LD |
R,
@LOC |
RH<-M[M[LOC]];
RL<-M[M[LOC]+1] |
4 |
1001
1111 |
9F |
|
LDB |
R,
@[R1] |
RL<-M[M[R1]]
indirect-register |
2 |
1001
1001 |
99 |
|
LD |
R,
@[R1] |
RH<-M[M[R1]];
RL<-M[M[R1]+1] |
2 |
1001
1101 |
9D |
|
MOV |
R1,
R2 |
R1<-R2 |
2 |
1011
0101 |
B5 |
|
STB |
Addr,
R |
M[addr]<-RL |
4 |
1001
0011 |
93 |
|
ST |
Addr,
R |
M[addr]<-RH;
M[addr+1]<-RL |
4 |
1011
0111 |
B7 |
|
STB |
R1,
R2 |
M[R2]<-R1L |
2 |
1111
1001 |
F9 |
|
ST |
R1,
R2 |
M[R2]<-R1H;
M[R2]<-R1L |
2 |
1111
1101 |
FD |
|
STB |
X,
R |
M[IX]<-RL;
IX++ |
2 |
1011
0001 |
B1 |
|
ST |
X,
R |
M[IX]<-RH;
IX++; M[IX]<-RL; IX++ |
2 |
1011
1101 |
BD |
|
STB |
+offset,
R |
M[B+offset]<-RL |
4 |
1100
0011 |
C3 |
|
ST |
+offset,
R |
M[B+offset]<-RH;
M[B+offset+1]<-RL |
4 |
1100
0111 |
C7 |
|
STB |
+[R1],
R |
M[B+R1]<-RL |
2 |
1100
0001 |
C1 |
|
ST |
+[R1],
R |
M[B+R1]<-RH;
M[B+R1+1]<- RL |
2 |
1100
0101 |
C5 |
|
STB |
@LOC,
R |
M[M[LOC]]<-RL |
4 |
1100
1011 |
CB |
|
ST |
@LOC,
R |
M[M[LOC]]<-RH;
M[M[LOC]+1]<-RL |
4 |
1100
1111 |
CF |
|
STB |
@[R1],
R |
M[M[R1]]<-RL |
2 |
1101
0001 |
D1 |
|
ST |
@[R1],
R |
M[M[R1]]<-RH;
M[M[R1]+1]<-RL |
2 |
1101
0101 |
D5 |
|
|
|
|
|
|
|
ALU |
|
|
|
|
|
|
ADD |
R1,
R2 |
A<-R1+R2 |
2 |
0000
0001 |
01 |
|
ADDC |
R1,
R2 |
A<-R1+R2+Carry |
2 |
0000
0101 |
05 |
|
SUB |
R1,
R2 |
A<-R1-R2 |
2 |
0000
1001 |
09 |
|
SUBB |
R1,
R2 |
A<-R1-R2-Carry |
2 |
0000
1101 |
0D |
|
AND |
R1,
R2 |
A<-R1
& R2 |
2 |
0001
0001 |
11 |
|
OR |
R1,
R2 |
A<-R1
| R2 |
2 |
0001
0101 |
15 |
|
XOR |
R1,
R2 |
A-<R1
^ R2 |
2 |
0001
1001 |
19 |
|
NOT |
R |
A<-~R |
2 |
0001
1101 |
1D |
|
|
|
|
|
|
|
|
Data
manip. |
|
|
|
|
|
|
SHL |
R |
A<-R*2;
carry<-overflow |
2 |
0010
0001 |
21 |
|
SHR |
R |
A<-R/2;
carry<- underflow |
2 |
0010
0101 |
25 |
|
ROTL |
R |
A<-R*2
+ carry |
2 |
0010
1001 |
29 |
|
ROTR |
R |
A<-R/2
+ (carry*2^16) |
2 |
0010
1101 |
2D |
|
|
|
|
|
|
|
Flow control |
|
|
|
|
|
|
JMP |
R |
PC<-
r |
2 |
0100
0001 |
41 |
|
JMP |
Immed |
PC<-immed |
3 |
0100
0010 |
42 |
|
JMPZ |
R |
IF
(Z) PC <- R
|
2 |
0100
0101 |
45 |
|
JMPC |
R |
IF
(C) PC <- R |
2 |
0100
1001 |
49 |
|
JMPN |
R |
IF
(N) PC <- R |
2 |
0100
1101 |
4D |
|
JMPO |
R |
IF
(O) PC <- R |
2 |
0100
0110 |
46 |
|
JMPZ |
Immed |
IF
(Z) PC <- immed |
3 |
0100
1110 |
4E |
|
JMPC |
Immed |
IF
(C) PC <- immed |
3 |
0101
0010 |
52 |
|
JMPN |
Immed |
IF
(N) PC <- immed |
3 |
0101
0110 |
56 |
|
JMPO |
Immed |
IF
(O) PC <- immed |
3 |
0101
1010 |
5A |
|
CALL |
R |
PUSH(PC);
PC <- R |
2 |
0101
0001 |
51 |
|
CALL |
Immed |
PUSH(PC);
PC <- immed |
3 |
0101
1110 |
5E |
|
RET |
|
PC
<- POP() |
1 |
0101
0000 |
50 |
|
RETI |
|
FLAGS
<- POP(); PC <- POP() |
1 |
0101
0100 |
54 |
|
PUSH |
R |
M[SP]<-RH;
SP++; M[SP]<-RL; SP++ |
2 |
0101
0101 |
55 |
|
POP |
R |
SP--;
RL<-M[SP]; SP--; RH<-M[SP] |
2 |
0101
1101 |
5D |
|
PUSHB |
R |
M[SP]<-RL;
SP++ |
2 |
0110
0001 |
61 |
|
POPB |
R |
SP--;
RL<-M[SP] |
2 |
0110
0101 |
65 |
|
|
|
|
|
|
|
I/O |
|
|
|
|
|
|
IN |
R |
RL
<- PORT[port] |
2 |
0110
1001 |
69 |
|
OUT |
R |
PORT[F[0..3]]
<- RL |
2 |
0110
1101 |
6D |
|
SETP |
Immed |
F[0..3]
<- immed
F register includes PORT# |
2 |
0111
0001 |
71 |
|
|
|
|
|
|
|
MISC |
|
|
|
|
|
|
NOP |
|
No
operation |
1 |
0000
0000 |
00 |
|
HALT |
|
Stop |
1 |
0000
0100 |
04 |
|
ESC |
|
Next
byte is FPU instruction |
1 |
0000
1000 |
08 |
|
SIM |
Immed |
F[8..11]
<- immed |
2 |
0011
0001 |
31 |
|
EI |
|
Enable
interrupts |
1 |
0011
0000 |
30 |
|
DI |
|
Disable
interrupts |
1 |
0011
0100 |
34 |
|
ACKI |
|
Acknowledge
interrupt |
1 |
0011
1000 |
38 |
|
|
|
|
|
|
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