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Homeworks

Progress Report 1

Progress Report 2

Final Report

EE 540, Winter 2012
VLSI Testing

Homeworks

Tentatively there will be no homework assignments this quarter. Class grade will be based on project work described below.

Project

There is essentially only one project for the quarter with 2 progress reports and 1 final report submitted based on the schedule below. The project proceeds as a research project with progress report 1 on comprehensive literature review, progress report 2 on design and simulation of a specific hardware security scheme, and final report on FPGA implementation of the chosen scheme.

Security project description

AES standard document (NEW)

Representative paper on AES implementation

Another paper on VLSI architectures for AES

Representative paper on side channel attacks of AES in FPGA

Slides on selected methods for side channel attacks

Paper on differential fault attack (NEW)

IEEE Hardware-Oriented Security and Trust (HOST) symposium

Altera Stratix IV GX FPGA, 530 Edition

The FPGA we will use to implement the class project is a gift from Altera Corporation. Note that the "530 Edition" does matter so when development kit, design information, and other documentation are downloaded from Altera web site, please make sure that they are for the 530 Edition.

http://www.altera.com/products/devkits/altera/kit-siv-gx.html

This web page also includes design examples.

Altera also provides an additional link for software even though the above page should have all the tools for design.

http://www.altera.com/products/software/sfw-index.jsp

Progress Report 1 (20% of course grade)

Literature review of attack methods, especially side channel attack methods, on AES implementations, including those using FPGAs.

Use the technical report format specified in the ITC Call for Papers below.

Page limit for this report is 5 pages.

Due no later than 5 PM, Wednesday 02-01

Turn in your progress report electronically at the URL posted on the main class web site.

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Progress Report 2 (30% of course grade)

Select and design one AES encryptor ONLY as a case study, then consider one or two side-channel attack methods on this specific architecture and implementation. You maydownload and use an existing AES encryptor design from the web. Modify the design to resist these attacks.

The report needs to include:

1.Original architecture design.

2.Discussion of one or two side-channel attack methods.

3. Modified design and simulation results to demonstrate that the revised architecture can resist the chosen one or two side-channel attack methods above.

The entire report, including the literature review already completed in Progress Report 1 above, is limited to 8 pages using the IEEE conference paper format. You will need to edit the literature review in Report 1 to reduce its length (to maximum 3 pages) so that the main part of Progress Report 2 is on the architecture design and simulation results mentioned above.

IMPORTANT NOTE:

Make sure that your Verilog code will be implementable on the FPGA so that you do not need to re-code to get hardware results for the Final Report.

Due no later than 5 PM, Monday 02-27

Turn in your progress report electronically at the URL posted on the main class web site.

Final Report and Presentation

Program the secured design (resistant to one or two methods of side-channel attacks) in Progress Report 2 onto the FPGA. Collect hardware results to demonstrate that the FPGA resists the chosen attack(s). Compare these results with the simulated results in Progress Report 2. Discuss differences. Discuss limitations of your secured design method.

The Final Report is limited to 10 pages using the IEEE conference paper format and includes sections from the work done in class, expected in regular conference papers:

1. Introduction and Problem Statement (from Report 1), limited to 1 page.

2. Literature review (from Report 1), limited to maximum 2 pages.

3. Chosen attack method(s) and architecture design for resistance (from Report 2), limited to 3 pages (more if you do not use up the 10-page limit).

4. Simulation results to demonstrate attack resistance (from Report 2), limited to 1 page.

5. Experimental hardware results from FPGA to demonstrate attack resistance, and comparison to simulation results, limited to 1.5 page (more if you do not use up the 10-page limit).

6. Discussion of advantages, disadvantages, and limitations of your architecture design in attack resistance, limited to 0.5 page.

7. Conclusion and References, limited to 1 page.

Report (40% of course grade): Due no later than 5 PM, Sunday 03-11

Presentation (10% of course grade): Due no later than 5 PM, Sunday 03-11

Turn in your final report and presentation electronically at the URL posted on the main class web site.

Progress Reports and Final Report requirements:

The formal written reports should follow the paper guideline used for conferences and journals. The Call for Papers for the International Test Conference 2010 is given as an example of the paper writing requirements. Note the absolute limit of 10 pages maximum (including figures and references, in 2-column format), which will apply to your submitted reports. You may want to use the ITC guide to authors to prepare your report and presentation. You can look at examples of actual ITC papers by searching IEEExplore.

Technical writing guidelines and requirements apply. For example, the References section must be included if other works are referred to. Each report must be typed and the figures should be done using computer-aided tools. Each entire report must be submitted electronically as one file (preferably in pdf format).

Project Presentation requirements:

The presentation of the report to the entire class will be scheduled during the time set by the University as final exam time for the course. Following typical conference presentation schedules, each presentation is allocated 20 minutes: 15 minutes for the talk and 5 minutes for questions from the audience. The 15-minute presentation is strictly enforced: 1 point will be deducted from the 10 total points assigned to the presentation if the speaker runs over time. Each team will be represented by only one speaker. The presentation will be given in electronic PowerPoint format.

The presentation should follow the outline of the report described above, with most of the time (at least 10 of the 15 minutes) devoted to your own work (i.e. do not spend most of the time talking about other previous works).

There are many guides to presentation: how to prepare the slides and how to present the talk. Two examples are provided for your use below (materials used by permission):

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Contact the instructor at: manisoma@u.washington.edu