Electrical Engineering

People > Faculty

Mani Soma


Mani Soma
Professor
Integrated Systems Research Group
Sieg Hall 219
Box 352500
University of WA
Seattle, WA 98195-2500

Phone: (206) 897-1783
E-mail: manisoma@u.washington.edu


[Biosketch] [Honors] [Research Interests] [Selected Publications] [Recent Conference Papers] [Patents] [Recent Grad Students] [Courses]


Biosketch

Mani Soma quickly escaped the university system with the standard set of degrees but just as quickly discovered that he was not up to any realistic industry challenge. Returning to the make-believe world of academia, he found a small niche area in mixed analog-digital system testing and published several inconsequential papers before the competition got tough. He is well known as a team builder and team player: the list of people he has cooperated with is just as long as and identical to the list of people who will never cooperate with him again. After a short stint as a notoriously incompetent part-time administrator, he now cooks, gardens, and teaches folk dancing. He continues to be a living proof of G. Bernard Shaw's dictum: "My reputation increases with every failure."

Honors

IEEE Fellow, "For contributions to mixed analog-digital system design-for-test."
Inventor Recognition Award, Semiconductor Research Corp., 2000, 2003.
Technical Excellence Award, Semiconductor Research Corp., 2004.

Research Interests

Design-for-test and Design-for-reliability techniques for integrated circuits and systems, with a strong focus on mixed-signal systems and distributed sensor systems.

Design methodologies and test techniques for high-frequency digital and communication systems.

Reliability characterizations and modeling for IC systems.

Research and Education Projects

Mixed-Signal On-chip Test Techniques, SRC

Scalable Design and Test Methods for RF Systems, NSF

Selected Recent Publications

T.J. Yamaguchi, M. Ishida, M. Soma, L. Malarsie, H. Musha, “Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division,” J. of Electronic Testing: Theory and Applications, vol. 19, no. 2, pp. 183-194, Apr. 2003.
K. Rahimi and M. Soma, “Layout Driven Synthesis of Multiple Scan Chains,” IEEE Trans. CAD, vol. 22, no. 3, pp. 317-326, March 2003.
T.J. Yamaguchi, M. Soma, M. Ishida, T. Watanabe, and T. Ohmi, “Extraction of Instantaneous and RMS Sinusoidal Jitter Using an Analytic Signal Method,” IEEE Trans. CAS-II, vol. 50, no. 6, pp. 288-298, June 2003.
T.J. Yamaguchi, M. Soma,  J.P. Nissen, D.E. Halter, R. Raina, and M. Ishida, “Skew Measurements in Clock Distribution Circuits Using an Analytic Signal Method,” IEEE Trans. CAD, vol. 23, no. 7, pp. 997-1009, July 2004.
K.A. Taylor, B. Nelson, A. Chong, H. Lin, E. Chan, M. Soma, H. Haggag, J. Huard, and J. Braatz, “CMOS Built-in Test Architecture for High-Speed Jitter Measurement,” IEEE Trans. Instrumentation & Meas., vol. 54, no. 3, pp. 975-987, June 2005.
Q. Wang, Y. Tang, and M. Soma, “Method to Measure RF Transceiver Bandwidth in the Time Domain,” IEEE Trans. Instrumentation & Meas., vol. 55, no. 3, pp. 982-988, June 2006.

Recent Conference Papers

M. Soma, W. Haileselassie, and J. Sherrid, “Measurement of Phase and Frequency Variations in Radio-Frequency Signals,” in Proc. IEEE VLSI Test Symposium, April 28 – May 2, 2003, Napa Valley, CA.
T. Yamaguchi, M. Soma. “Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements,” in Proc. IEEE International Test Conf., September 2003, Charlotte, NC.
H. Lin, K. Taylor, A. Chong, E. Chan, M. Soma, H. Haggag, J. Huard, and J. Braatz. “CMOS Built-In Test Architecture for High-Speed Jitter Measurement,” in Proc. IEEE International Test Conf., September 2003, Charlotte, NC.
Q. Wang, Y. Tang, and M. Soma. “GHz RF Front-End Bandwidth Time Domain Measurement,” in Proc. IEEE VLSI Test Symposium, April 26 – 29, 2004, Napa Valley, CA.
M. Soma, B. Ngo, J. Yan, R.D. Christie, and E.A. Riskin. “Hands-on Circuit Design and Test Laboratory for Distance Learning in Electrical Engineering,” in Proc. ASEE Annual Conference, June 20-23, 2004, Salt Lake City, UT.
M. Ishida, K. Ichiyama, T.J. Yamaguchi, M. Soma, M. Suda, T. Okayasu, D. Watanabe, and K. Yamamoto, “A Programmable On-chip Picosecond Jitter Measurement Circuit without a Reference Clock Input,” in Proc. IEEE International Solid-State Circuits Conf., February 2005, San Francisco, CA.
T. Yamaguchi, M. Ishida, M. Soma, K. Ichiyama, K. Christian, K. Ohsawa, and M. Sugai, “A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems,” in Proc. IEEE International Test Conf., October 26-28, 2004, Charlotte, NC.
Q. Wang and M. Soma, “RF Front-end System Gain and Linearity Built-in Test,” in Proc. IEEE VLSI Test Symposium, April 30 - May 4, 2006, Berkeley, CA.
M. Soma, “High-frequency on-chip measurements: Challenges and Approaches,” in Proc. IEEE North Atlantic Test Workshop, May 10-12, 2006, Essex Junction, VT. [Invited Talk]
K.Ichiyama, M. Ishida, T. Yamaguchi, and M. Soma, “A Real-time Delta-time-to-Voltage Converter for Clock Jitter Measurement,” in Proc. IEEE International Test Conf., October 24-26, 2006, Santa Clara, CA.
T. Yamaguchi, S. Iwamoto, M. Ishida, and M. Soma, “A Study of Per-pin Timing Jitter Scope,” in Proc. IEEE International Test Conf., October 24-26, 2006, Santa Clara, CA.
M. Ishida, T.J. Yamaguchi, and M. Soma, “A Method for Testing Jitter Tolerance of SerDes Receivers Using Random Jitter,” in Proc. Int. Engr. Consortium DesignCon 2007, January 29 – February 1, 2007, Santa Clara, CA. [DesignCon Paper Award winner]
K. Ichiyama, M. Ishisa, T. Yamaguchi, and M. Soma, “An on-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter,” in Proc. IEEE Int. Symp. on Circuits & Syst., May 27-30, 2007, New Orleans, LA.
M. Ishida, K. Ichiyama, T.J. Yamaguchi, M. Soma, M. Suda, and T. Okayasu, “On-chip Circuit for Measuring Data Jitter in the Time or Frequency Domain,” in Proc. IEEE RF IC Symp., June 3-5, 2007, Honolulu, HI.
K. Ichiyama, M. Ishida , T.J. Yamaguchi and M. Soma, “Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter,” in Proc. IEEE Custom Integrated Circuits Conf., September 16-19, 2007, San Jose, CA.
K. Ichiyama, M. Ishida , T.J. Yamaguchi and M. Soma, “Data Jitter Measurement using a Delta Time-to-Voltage Converter Method,” in Proc. IEEE International Test Conf., October 22-24, 2007, Santa Clara, CA.
T.J. Yamaguchi, H.X. Hou, K. Takayama, D. Armstrong, M. Ishida, and M. Soma, “An FFT-Based Jitter Separation Method for High-Frequency Jitter Testing with 10X Reduction in Test Time,” in Proc. IEEE International Test Conf., October 22-24, 2007, Santa Clara, CA.

Recent Patents

"Testing apparatus and testing method," United States Patent #7,136,773, awarded November 14, 2006; Inventors: M. Ishida, T. Yamaguchi, and M. Soma.
"Processing apparatus, processing method and position detecting device," United States Patent #7,193,728, awarded March 20, 2007; Inventors: M. Ichikawa, T. Yamaguchi, M. Yoshida, and M. Soma.
"Apparatus for and method of measuring jitter," United States Patent #7,203,229, awarded April 10, 2007; Inventors: M. Ishida, T. Yamaguchi, and M. Soma.
"Electronic device with integrally formed light emitting device and supporting member," United States Patent #7,253,443, awarded August 7, 2007; Inventors: M. Yoshida, T. Yamaguchi, M. Ichikawa, and M. Soma.
"Probability estimating apparatus and method for peak-to-peak clock skews," United States Patent #7,263,150, awarded August 28, 2007; Inventors: M. Ishida, T. Yamaguchi, and M. Soma.
"Measurement instrument and measurement method," United States Patent #7,305,025, awarded December 4, 2007; Inventors: T. Yamaguchi, M. Ishida, and M. Soma.

Recent Graduate Students

Stephen Wang

Ken Blakkan

Te-Yu Kao

Courses