TCSS 372A Computer Architecture (Fall 2009)

Course Description:      

Covers the micro architecture level of machine design and advanced architecture features for performance enhancement. Subjects include I/O, bus, memory and CPU design, hardware support for operating systems, CISC/RISC architectures, and parallelism.
(CSS 372 Course Objectives)
Prerequisites: a minimum grade of 2.0 in both TCSS 371 and TCSS 342.


TTh 4:15 - 6:20   CP105


Larry A. Crum, Professor Emeritus
Office: Cherry Parkes 224
Office Hours:   TTh 9:30 - 10:15,   TTh 2:30 - 4:00,   & by Appointment
Phone: (253) 692-5866


Computer Organization and Architecture      
Designing for Performance

Eighth Edition (2009)

William Stallings
Pearson Prentice Hall  
ISBN-13: 978-0-13-608860-8

This book is about the structure and function of computers. Its purpose is to present, as clearly and completely as possible, the nature and characteristics of modern-day computer systems.

A computer system, like any system, consists of an interrelated set of components. The system is best characterized in terms of structure - the operation of the individual components. Futhermore, a computer's organization is hierarchical. Each major component can be further described by decomposing it into its major subcomponents and describing their structure and function. For clarity and ease of understanding, this hierarchical organization is described in this book from the top down:
  • Computer System: Major components are processor, memory, and I/O,

  • Processor: Major components are control unit, registers, ALU, and instruction,

  • Control Unit: Provides control signals for the operation and coordination of all processor components. Traditionally, microprogramming implementation has been used. More recently, microprogramming has been less prominent but remains an implementation technique.



Introduction to Computing Systems, From Bits & Gates to C & Beyond, Yale N. Patt & Sanjay J. Patel, McGraw Hill, 2004
Computer Organization and Design: The Hardware/Software Interface, (Fourth Edition), David A. Patterson & John L. Hennessy, Morgan Kaufmann Publishers (Elsevier Inc.), 2009
Structured Computer Organization (5th Edition), Andrew S. Tannenbaum, Pearson Prentice Hall, 2006
Computer Systems (Third Edition), J. Stanly Warford, Jones & Bartlett Publishers, 2005
LogicWorksTM 5 Interactive Circuit Design Software, Capilano Computing, Pearson Prentice Hall, 2004
Digital Design: Principles and Practices Package (4th Edition), John F. Wakerly, Prentice Hall, 2005
The Art of Electronics (2nd Edition), Paul Horowitz and Winfield Hill, Cambridge press, 1989

Class Schedule:

  Week:       Date                            Topic     Reading Lecture Slides/References Assignment (Due 2nd period after assigned
                        30% deduction after due class
                        50% deduction next class)
        1: Thur - Oct 1 Organization, Registers, Data Paths, Timing, Buses, Stacks, Memory Maps Chap 0, 2.1, 2.4-2.5, 3.1-3.4, 3.A Introduction/Review Slides
Homework Format

        2: Tue - Oct 6 ISA Comparisons, Addressing, RISC & CISC Chap 13.1,13.4 ISA, RISC/CISC Slides HW1:     Context Switching
Thur - Oct 8 Arithmetic, Floating Point Chap 9.3-9.5 Arith, FP Slides HW2: 9-15,18,20,24,31,38,39,40

        3 : Tue - Oct 13 Memory Hierarchy: Internal Memory & Issues, Cache Memory Systems Chap 5.1, 5.3, 4.1-4.2 Memory & Direct Cache
Thur - Oct 15 Cache Memory Systems Chap 4.3 Cache Memory HW3: 5-2,8     4-1,5,11,23

        4 : Tue - Oct 20 Error Detection/Correction Chap 5.2 Hamming Code HW4: 5-11,12

Thur - Oct 22 Midterm (Thru Cache Memory Systems) Midterm 1 Solution

        5 : Tue - Oct 27 External Memory, Memory Sharing, Interrupts Chap 6, 7.1-7.4 External Memory Midterm - Problem 6 (Due 10/29)

Thur - Oct 29 Interrupts, DMA, Channels, Contexts, Context Switching Chap 7.5-7.6 DMA & Channels HW5: 6-3,4     7-9,10,11,12(use Crum's definition of cycle stealing)

        6 : Tue - Nov 3 Operating System Support: Scheduling, Multi-Tasking/Threading, Memory Management Chap 8.1- 8.3 OS support HW6a: 8-8,15,17

Thur - Nov 5 Mem Man:Paging, Virtual Memory; Pipelining Chap 12.4 Pipelining HW6b: 12-7,10

        7 : Tue - Nov 10 RISC specific: Register Files, Register Optimization Chap 13.2-13.3, 13.5 RISC Pipelining

Thur - Nov 12 No Class

        8 : Tue - Nov 17 RISC Specific: Pipelining; Review MIPS Pipelining

Thur - Nov 19 Midterm (Thru Nov 5th Material) Midterm 2 Solution

        9 : Tue - Nov 24 Superscalar Machines (class cancelled) Chap 14.1-14.2 Superscalar Machines

Thur - Nov 26 Thanksgiving

        10 : Tue - Dec 1 Superscalar Machines Chap 14.1-14.2 Superscalar Machines HW7: 12- 7,8     13-6,7     MIPS     14-5,6

Thur - Dec 3 Predication, Speculation, & Software Pipelining (IA-64 or EPIC) Chap 21.1-21.5 IA-64 EPIC Architecture

        11 : Tue - Dec 8 Control Units: Hardwired State Machines vs Microprogrammed, Multithreading, Clusters Chap 15.1-15.4, 16.1-16.3, 17.4-17.5 Control Units
Parallel Processing

Thur - Dec 10 Multicore Machines, Recap Chap 18.1-18.4 Multicore Machines
Final Prep

        12 : Thur - Dec 17 Final Exam Final Exam Solution


Midterms (20% each), Final Exam (25%), Homework (25%), Class Contribution (10%)

Characteristics of an A student - Work is outstanding in quality, and shows unusual understanding, insight, and creativity. It is consistently presented very clearly and professionally. (S)he consistently contributes to the understanding of others.
Characteristics of a B student - Work done is complete, predominance of it is correct, and it is well presented. (S)he contributes to the understanding of others.
Characteristics of a C student - Work is basically complete and correct, and it is presented coherently. The student is prepared to use the material in the next course but will likely need additional study in the area.


Students are encouraged to collaborate regularly with colleagues to gain a deep understanding of the material, and to gain insight on options for problem solutions. Submitted are to display individual knowledge and accomplishment. Any significant contribution in a submission must be acknowledged and the responsible student or source given due credit. See

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