Error Description: The fourth line of the first Code Example reads,

cout << “The bitwise Anding of 0x55 and 0xAA  =  ,”  outC << endl;

• Understand the logical operation of the Type 'D' flip-flop (D-FF)
• Describe how binary counters, frequency dividers, shift registers and storage registers can be built from D-FF's.

1. 4 input variables: A, B, C, D = 16 cells
2. 3 input variables: A, B, C = 8 cells
3. 5 input variables: A, B, C, D, E = 32 cells

The number of cells in the K-map equals the number of possible combinations of input variable states. For example,

1. 3 input variables: A, B, C = 8 cells
2. 4 input variables: A, B, C, D = 16 cells
3. 5 input variables: A, B, C, D, E = 32 cells

1- The Caption should read, Figure 4.13: Magnified view of the clock input and Q0 output part of Figure 4.12.

2- The last paragraph on the page should not be part of the caption to Figure 4.13. It should read,

Assume that we’ve just asserted RESET and outputs Q₀ through Q₃ are all 0. There are no clock pulses coming in at the CLK input on the left. The circuit is quiet and life is good. Suddenly, there’s a knock at the door. Oops, wrong book. Suddenly, a single clock pulse is received at the CLK input. Since the ~Q output = 1, the D input is 1, so after the clock pulse, the Q output of the leftmost D-flop goes to 1. The ~Q output goes from 1 to 0. That’s a falling edge, so there is no change at the second D-flop.

• It can exist in a finite set S of states s.
• There is an initial state s₀ that is a member of set S.
•  A finite set I of inputs i
• A next state function d = d(s,i) that maps the present state values and the inputs into the next state in S.
• An output function, f = f(s,i)          

• It can exist in a finite set S of states s;
• There is an initial state s₀ that is a member of set S;
•  A finite set I of inputs i;
• A next state function d = d(s,i) that maps the present state values and the inputs into the next state in S;
• An output function, f = f(s,i); 

Figure 5.7: State transition diagram for a circuit that detects 3 or more successive 1's in a serial bit stream.

Here we have 3 states, 00, 10, and 01, respectively. The arrows represent the state transitions on the clock edge. Associated with each arrow are two numbers separated by a forward slash. The first number is the state of the input bit at the time of the rising edge of the clock and the second number is the output signal, T, which goes TRUE if three or more successive 1’s are detected in the bit stream.

In this case, the clock signal that we would use would likely be the clock that the system is using to synchronize with the data bit stream. Thus, a new data bit would appear on every rising edge of the clock.  Every time that a 0 bit appears the circuit returns to the 00 state, waiting for the arrival of a 1 bit. With the arrival of the first 1 bit the circuit transitions to state 10. If a second 1 bit arrives it transitions to state 01. If the second bit to arrive is a 0 bit, the circuit returns to state 00. However, if a third 1 bit arrives, the circuit asserts output T and returns to state 01 with the T bit set to 1. As soon as the next 0 bit arrives, the circuit returns to state 00. What is new in this example is the addition of an explicit output bit, T.

You might be wondering why we don’t have a fourth state, 11, which represents the arrival of 3 successive 1’s. This would also work, but it would be redundant, since the arrival of the third successive 1 bit also means that there has been two successive 1’s as well. Thus, we may remain in state 01 as long as 1’s are being received. We could, however, change the problem specification so that each group of three 1’s is a unique event. This would imply that a fourth state might be needed, depending upon what we intend to do after each group of three is received.

Correction: "Anext" should be at the D input to the top flip-flop and "A" should be at the Q output. Also, "Bnext" should be at the D input to the middle flip-flop and "B" should be at the Q output.

Correction: The word "or" should not be italicized between state machine and ASM.

Correction: Should read, Since the N/S traffic is a busy four-lane road and the E/W road is only two lanes, we can assume that the N/S road has a considerably higher traffic flow than the E/W road.

while (timer != 0)

 wait;

   timer = 5 seconds;

EW = yellow;

Should read, 

while (timer != 0)

 wait;

timer = 5 seconds;

EW = yellow;

Should read,  As long as neither of the E/W sensors detect a waiting car, the...

In Figure 6.16, this translates to a mechanism for independently accessing either the upper or lower memory chip of each page. With that addition, we could write a single byte to one or the other memory device and not corrupt the data in the other device.

Now, having said that, we could conceivably come up with a mechanism to overcome this limitation. For example, let’s assume that the processor wants to store a byte in one of the memory chips in Figure 6.16. It could first read the data from both chips into an internal storage area, then write the byte into the correct half of the 16-bit word and finally, it could write the result back out to both chips. This is an extremely costly operation to write a single byte. In practice, and as you’ll see in Chapter 7, we need to add a bit more to this circuit design so that byte-addressability within a larger memory word can be realized.

Error Description: The third and sixth sentences of paragraph #1 respectively read, 

1. This is called Little Endian organization.

2. This is called Big Endian organization.

1. This is called Little Endian organization.

2. This is called Big Endian organization.

A0 = 0: ~LDS = 1, ~UDS = 0

A0 = 1: ~UDS = 1, ~LDS = 0

A0 = 0: ~LDS = 1, ~UDS = 0

A0 = 1: ~LDS = 0, ~UDS = 1

Symbol-name Type Value Decl Cross reference line numbers

COMPARE LABEL 00000406 13 14.

START LABEL 00000400 11 12.

TEST LABEL 00000404 12 * * NOT USED * *

WAIT LABEL 00000408 14 * * NOT USED * *

COMPARE LABEL 00000406 13 14.

START   LABEL 00000400 11 12.

TEST    LABEL 00000404 12 * * NOT USED * *

WAIT    LABEL 00000408 14 * * NOT USED * *

ORG       $400             *Start of code

          MOVE.B    Y,D0    *Get the first operand

          ORG       $400    *Start of code

          MOVE.B    Y,D0    *Get the first operand